Polaris PowerLED Technologies: US-9305661-B2 (Reducing Bit Errors in the Nonvolatile Memory System)
FinishedWinner Announced
9305661 - Reducing Bit Errors in the Nonvolatile Memory System
Prize: $2000
Ended a month ago
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Participants are required to use the Pearl claim charting tool to generate submissions. Each participant can claim 30 free charts for patent 9305661.

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DOWNLOAD WINNING PRIOR ART HERE: https://www.unifiedpatents.com/insights/2025/5/28/9000-awarded-for-polaris-powerled-memory-controller-patents-prior-art
Unified is seeking prior art on at least claim 1 of US-9305661-B2, owned and asserted by Polaris PowerLED Technologies, LLC.
The '661 patent relates to a method and system for reducing bit error rates in nonvolatile memory devices by identifying and managing weak memory cells. The patent is involved in a declaratory judgement action with Micron. For more information on the patent:
https://portal.unifiedpatents.com/patents/patent/US-9305661-B2
View the Similar Documents (patents + scholarly publications) generated by Google Patents:
Patents: https://patents.google.com/?q=(~patent%2fUS9305661B2)&before=filing:20140903
NPL: https://patents.google.com/?q=(~patent%2fUS9305661B2)&before=filing:20140903&patents=false&scholar
Start Date: Tue Mar 18 2025 14:44:49 GMT+0000 (Coordinated Universal Time)
End Date: Sat Apr 26 2025 05:00:00 GMT+0000 (Coordinated Universal Time)
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