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Polaris PowerLED Technologies: US-9305661-B2 (Reducing Bit Errors in the Nonvolatile Memory System)

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9305661 - Reducing Bit Errors in the Nonvolatile Memory System
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Unified is seeking prior art on at least claim 1 of US-9305661-B2, owned and asserted by Polaris PowerLED Technologies, LLC. The '661 patent relates to a method and system for reducing bit error rates in nonvolatile memory devices by identifying and managing weak memory cells. The patent is involved in a declaratory judgement action with Micron. For more information on the patent: https://portal.unifiedpatents.com/patents/patent/US-9305661-B2 View the Similar Documents (patents + scholarly publications) generated by Google Patents: Patents: https://patents.google.com/?q=(~patent%2fUS9305661B2)&before=filing:20140903 NPL: https://patents.google.com/?q=(~patent%2fUS9305661B2)&before=filing:20140903&patents=false&scholar ** PLEASE READ THE RULES FOR THIS CONTEST BEFORE YOU DECIDE TO PARTICIPATE. ** ** TO QUALIFY FOR CONSIDERATION, A CLAIM CHART IS REQUIRED. ** ** PLEASE USE THE PROVIDED CLAIM CHART AS A TEMPLATE. LINK OR PROVIDE A PDF COPY OF THE CITED ART. ** ** PRIOR ART THAT HAS BEEN PREVIOUSLY CITED DURING PROSECUTION WILL NOT BE CONSIDERED. **

Start Date: Tue Mar 18 2025 14:44:49 GMT+0000 (Coordinated Universal Time)

End Date: Sat Apr 26 2025 05:00:00 GMT+0000 (Coordinated Universal Time)


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Micron v Polaris PowerLED.pdf

Unified Claim Chart Template.docx

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